Commonly assigned U.S. patent application Ser. No. 71,826, filed on Sept. 4, 1979, by H. L. Beranger, C. Marzin, D. M. Omet and J. L. Peter, entitled "Power Supply System for Monolithic Cells", now U.S. Pat. No. 4,295,210, relates to a monolithic memory where power dissipation has been reduced by applying to the selected cells a voltage higher than the supply voltage of non-selected cells, which is made possible by using current switching circuits.
The decoding and selection circuits as described in an article published in the IBM Technical Disclosure Bulletin, Vol. 20, No. 11A, April 1978, pages 4406 to 4408, generally use a driver transistor associated with each word line and an address decoding circuit with diodes, the driver transistor becoming conductive when the corresponding word line is selected. A resistor is connected to the transistor base and to the common point at the anodes of the decoder diodes in order to supply the selection current to the transistor base when the line is selected. At that time all diodes are off. If the line is not selected, at least one of the decoder diodes becomes conductive and the current in the resistor is deviated by the conducting diodes.
The disadvantage of such a circuit is that the resistor causes considerable power dissipation.